A typical technology for processing a PCI Express protocol is configured to use a buffer for storing data included in a received packet to guarantee the integrity of data in a transaction layer and a data link layer, a buffer for temporarily storing the data of a packet to be transmitted because the point of time which the completion of the data is guaranteed for is unclear, and a retransmission buffer for preparing for the case where it is impossible to become aware of the arrival of a transmitted packet until the packet is checked for errors at the destination and notification of the complete arrival of the packet is provided. These buffers are constructed using memory.
FIG. 1 is a block diagram showing the construction of a conventional apparatus for processing a PCI Express protocol. Referring to FIG. 1, a conventional process of processing a PCI Express protocol will be described below.
First, the reception flow controller 52 of a PCI Express transaction layer reception unit 50 periodically detects the size of the storage space of virtual channel memory 51, and transmits information about the size to the packet transmitter 82 of a PCI Express data link layer transmission unit 80. The packet transmitter 82 creates a flow control packet, and transmits the packet to a PCI Express physical layer 30 through a packet transmission interface 81. The PCI Express physical layer 30 attaches frame information to the flow control packet, and transmits the flow control packet with the frame information attached thereto to an upstream device 10 through a PCI Express link 20.
The upstream device 10 checks whether an available packet storage space is present in the virtual channel memory 51 of the PCI Express transaction layer reception unit 50, and creates a request packet if an available packet storage space is present in the virtual channel memory 51. The request packet created by the upstream device 10 reaches the PCI Express physical layer 30 through the PCI Express link 20. The PCI Express physical layer 30 removes the frame information from the packet, and transmits the frame information-free packet to a PCI Express data link layer reception unit 40. The PCI Express data link layer reception unit 40 receives a transaction layer packet TLP, that is, the request packet, through a packet reception interface 41 therein, and temporarily stores the transaction layer packet TLP in received packet buffer memory 42. When the overall packet has been stored, a received packet integrity checker 43 checks the integrity of the packet. If the packet is determined to be complete, the received packet integrity checker 43 transmits an acknowledgement signal indicating that an acknowledgement packet Ack DLLP can be transmitted to a packet transmitter 82 inside the PCI Express data link layer transmission unit 80.
The packet transmitter 82 creates an acknowledgement packet Ack DLLP, and transmits the packet to the PCI Express physical layer 30 through the packet transmission interface 81. The PCI Express physical layer 30 transmits the acknowledgement packet to the upstream device 10 through the PCI Express link 20.
When the integrity of the packet is verified by the received packet integrity checker 43, the packet inside the received packet buffer memory 42 is transmitted to the virtual channel memory 51 at the same that the acknowledgement packet is created and transmitted to the upstream device 10 as described above. A received packet checker 53 checks whether the packet is a packet which can be handled in an application device layer 60. If the packet a packet which can be handled in the application device layer 60, the received packet checker 53 creates the header of an acknowledgement packet, and transmits the header information to a transmission packet generator 72 inside the PCI Express transaction layer transmission unit 70. Furthermore, the received packet checker 53 directs the application device layer 60 to access data. The application device layer 60 stores data access results which were generated at a certain point of time, in transmission data alignment memory 73.
After recognizing the header and data part of response information for the request packet, the received packet checker 53 deletes the packet from the virtual channel memory 51. Since an available packet storage space is generated in the virtual channel memory 51 again after the deletion of the packet, the reception flow controller 52 transmits flow control information to the packet transmitter 82, the packet transmitter 82 creates a flow control packet and transmits the flow control packet to the PCI Express physical layer 30 through the packet transmission interface 81, and the PCI Express physical layer 30 attaches frame information to the flow control packet and transmits the flow control packet with the frame information attached thereto to the upstream device 10 through the PCI Express link 30.
The upstream device 10 receives an acknowledgement packet, creates the information of a flow control packet indicating whether storage can be performed on its own virtual channel memory, and transmits the flow control packet to the PCI Express physical layer 30 through the PCI Express link 20. This is transmitted to a packet receiver 44 through the packet reception interface 41 inside the PCI Express data link layer reception unit 40. The information of the flow control packet received by the packet receiver is transmitted to a transmission flow controller 71 inside the PCI Express transaction layer transmission unit 70, and will be used as information for determining whether an acknowledgement packet can be transmitted later.
When the data transmitted by the application device layer 60 is all stored in the transmission data alignment memory 73 and a signal which is determined to be transmitted by the transmission flow controller 71 transmitted to the transmission packet generator 72, the transmission packet generator 72 combines data stored in the transmission data alignment memory 73 with header information previously received from the received packet checker 53, and transmits resulting data to the packet sequence generator 85 of the PCI Express data link layer transmission unit 80. Furthermore, the packet sequence generator 85 attaches a sequence used for the upstream device 10 to determine the integrity of a transaction layer packet and a Cyclic Redundancy Code (LCRC) on a link to the front and rear ends of the response packet, respectively. The packet made to include the integrity information by the packet sequence generator 85 is transmitted to the PCI Express physical layer 30 through the packet transmission interface 81 and, at the same time, is temporarily stored in retransmission buffer memory 84. If an error occurs in the transmission of the packet and, therefore, the packet needs to be transmitted again, the data temporarily stored in the retransmission buffer memory 84 is transmitted again.
The acknowledgement packet transmitted to the PCI Express physical layer 30 is transmitted to the upstream device 10 through the PCI Express link 20. The upstream device 10 checks the integrity of the received acknowledgement packet, loads information about checking results on an integrity acknowledgement packet Ack/Nak DLLP, and transmits the integrity acknowledgement packet with the information loaded thereon to the PCI Express physical layer 30 through the PCI Express link 20. The PCI Express physical layer 30 removes the frame information from the received acknowledgement packet, and transmits the frame information-free acknowledgement packet to the packet receiver 44 through the packet reception interface 41. If the packet received by the packet receiver 44 is an Ack (Acknowledge) packet, a signal directing the response packet temporarily stored in the retransmission buffer memory 84 of the retransmission processor 83 to be removed. In contrast, if the received packet is a Nak (negative acknowledge) packet, the retransmission processor 83 is directed to retransmit the acknowledgement packet temporarily stored in the retransmission buffer memory 84.
Furthermore, if there has been no Ack or Nak response in the packet receiver 44 for a predetermined period of time, the retransmission processor 83 is directed to transmit the packet temporarily stored in the retransmission buffer memory 84 again. This packet retransmission process is repeated until an Ack packet is received. The PCI Express link 20 is reset every four times.
In order to prepare for the case where in the above process, the request packet created by the upstream device 10 is a packet for reading data in the application device layer 60 and the length of the data is not uniform, the received packet buffer memory 42 needs to have data storage memory having a capacity equal to or greater than 4 Kbyte, that is, the greatest length which was defined in the PCI Express specifications, and the virtual channel memory 51 needs to also have data storage memory having a capacity equal to or greater than 4 Kbyte. In order to prepare for the case where in the above-described process, the request packet created by the upstream device 10 is a packet for reading data in the application device layer 60 and the length of the data is not uniform, the transmission data alignment memory needs to have memory having a capacity equal to or greater than 4 Kbyte so as to store data and the retransmission buffer memory 84 needs to also have memory having a capacity equal to or greater than 4 Kbyte.
In the technology for processing a PCI Express protocol, packets for memory transaction transmission and reception are assumed to be processed in the manner of bust transmission or block unit transmission in the memory transaction transmission and reception, so that the lengths of the packets cannot be predicted, with the result that buffers needs to be used as described above.
However, in the case of a PCI Express device processing only Input/Output (I/O) transactions, an actually used packet includes one data payload, so that the length of the packet cannot be predicted. With regard to the frequency of reception of packets, a counterpart device (master device) which created an input/output transaction creates a subsequent packet after waiting for a response, so that the device does not create packets for which responses have not been received at the same time.
As an example, when a PCI Express device which receives only an input/output transaction is used for the expansion of a 500 Mbps serial port in the PCI Express, a bandwidth equal to or less than ⅕ of the bandwidth (in the case of 1×, 2.5 Gbps) provided by the PCI Express is used, so that the frequency of packets is not high even when the time taken until a packet generated at an actual PCI Express link is received after being transmitted is sufficiently taken into account.
In this case, when the conventional apparatus for processing a PCI Express protocol is used, a large amount of memory is unnecessarily used. In the case where an apparatus for processing a PCI Express protocol (engine) and an application device (engine) are integrated in a single chip, the apparatus for processing a PCI Express protocol occupies unnecessary memory in an actual operation, so that a problem arises in that the amount of memory which needs to be occupied by the application device is relatively reduced. Accordingly, in order to overcome this problem, some other devices may be selected for such integration.
As described above, in the conventional apparatus for processing a PCI Express protocol, even a device which processes predictable transactions needs to use memory in a uniform manner, so that a problem arises in that lack of memory resources may be caused to an application device.
Furthermore, due to different memory interfaces of respective manufacturing processes resulting from the variety of integration processes, methods of operating memory, that is, memory access protocols and operating speeds, are different from one another, so that a problem may occur in that the design of the apparatus for processing a PCI Express protocol needs to bP changed to fit a memory interface.
In an input/output transaction used in a low-speed PCI Express, the amount of data to be processed in a request packet or a reading packet is fixed to 4 bytes, 4 or more—Kbyte memory maintained in the received packet buffer memory and the virtual channel memory 51 used in the conventional apparatus for processing a PCI Express protocol shown in FIG. 1 is not actually required, and 4 or more —Kbyte memory maintained in the transmission data alignment memory 73 is not actually required also. Furthermore, in the case of an input/output transaction, although the upstream device 10 having created a request packet receives an acknowledgement packet, checks the acknowledgement packet for integrity, processes information included in the acknowledgement packet and creates a subsequent request packet, a trouble is not caused to the bandwidth. Moreover, in order to create a subsequent request packet, the request packet is created after the virtual channel memory 51 has been checked for a data storage space. Accordingly, in order to determine whether to retransmit an acknowledgement packet created by the packet sequence generator 85, if the reception flow controller 52 is aware of information about the reception of an acknowledgement packet Ack DLLP transmitted to the retransmission processor 83 by the packet receiver 44, the reception flow controller 52 directs the packet transmitter 82 to transmit a flow control packet, including information indicating that a subsequent request packet can be received, only when an acknowledgement packet generated by the packet sequence generator 85 has completely arrived, so that it is not necessary to use the retransmission buffer memory 84.